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arm: mx6: gw_ventana: Change clock init to enable NAND related clocks
author
Stefan Roese
<
[email protected]
>
Thu, 4 Dec 2014 12:04:06 +0000
(13:04 +0100)
committer
Stefano Babic
<
[email protected]
>
Fri, 19 Dec 2014 14:32:14 +0000
(15:32 +0100)
Otherwise NAND booting is likely to fail. Since this disables the NAND related
clocks and SPL can't load the main U-Boot from NAND.
This problem was introduced with this patch:
e25fbe3f
(gw_ventana: Move the DCD settings to spl code)
Signed-off-by: Stefan Roese <
[email protected]
>
Cc: Fabio Estevam <
[email protected]
>
Cc: Tim Harvey <
[email protected]
>
Cc: Stefano Babic <
[email protected]
>
Reviewed-by: Fabio Estevam <
[email protected]
>
board/gateworks/gw_ventana/gw_ventana_spl.c
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diff --git
a/board/gateworks/gw_ventana/gw_ventana_spl.c
b/board/gateworks/gw_ventana/gw_ventana_spl.c
index d6a584745bd168edc8e57a8cadd869c3a9351dd6..97128127fbe741f2393faeba06d1c4ff40a23238 100644
(file)
--- a/
board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/
board/gateworks/gw_ventana/gw_ventana_spl.c
@@
-401,7
+401,7
@@
static void ccgr_init(void)
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
- writel(0x
00FFF300, &ccm->CCGR4);
+ writel(0x
FFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}